NEC Corporation (NEC) and NEC Electronics Corporation (NEC
Electronics) announced that they have succeeded in the development
of a new desi gn method for large-scale integrations (LSIs) with
more than 50 million transistors, operating at a speed of several
hundred megahertz. NEC and NEC Electronics’ new design method
introduces a “Border Movi ng Method” into the design process, which
completely eliminates the n eed for the budgeting process and
re-designing of hierarchical blocks, dramatically shortening the
total length of time required for backend design for large scale
and high speed LSI to 1/3 of the conventional design method.
With large scale LSI design, all of the LSIs are usually not
designed simultaneously (flat design) as it is difficult for
designers to grasp the complete picture and there is a high
probability that the design will exceed the limitations of
available tools. It is therefore common to deploy the “hierarchical
design method.” With this method, an LSI is divided into several
hierarchical blocks. The blocks are design ed independently and are
later assembled into one LSI. Each block is small enough to be
handled by a designer and available tools. In addition, the divided
blocks can be concurrently designed by several desig ners, making
this method extremely effective for implementing large scale LSIs
in short time frames.
However, there are some downfalls to this method. In
particular, “Budgeting (timing constraint budgeting)”is an
inevitable bottleneck in the hierarchical design method. Budgeting
is carried out in order to impose a timing constraint on a signal
path between two hierarchical blocks. However, the constraint
cannot be considered for the entire path, it can only be considered
for the three partial signal paths separ ately: 1) the signal path
inside one hierarchical block, 2) the signal path between two
hierarchical blocks and 3) the signal path inside another
hierarchical block. In other words, each of the three partial paths
must fulfill its own timing constraint and the ent ire signal path
must satisfy the original constraint at the same time. It is only
after the design of the blocks is completed that the desi gners can
tell whether the timing constraint for the signal path between the
blocks can be satisfied. If the constraint cannot be satisfied, the
designers must repeatedly assign a different timing constraint to
the blocks and design them all over again from scr atch, until the
entire signal path fulfills its timing constraint. Thus, budgeting
is a very difficult and time-consuming process even for one signal
path. Typical large scale and high speed LSIs have several tens of
thousands of signal paths connecting hierar chical blocks.
Budgeting of a large number of signal paths takes seve ral months
and lengthens the total LSI design period.
NEC and NEC Electronics’ new design method introduces a
“Border Moving Method.” After designing hierarchical blocks, the
method modifies the boundary of blocks and moves partial signal
paths out of the blocks. These partial signal paths, which used to
reside inside the block s, and the partial signal path connecting
the blocks are then combined into one signal path. As a result,
only the delay for the single signal path has to be considered,
eliminating the need for budgeting and re-designing hierarchical
blocks. This breakthrough research result has been achieved through
the intr oduction of an intelligent algorithm that minimizes the
modification o f the boundary, and which has been elaborated enough
to allow practical application in the design of real large-scale
LSI.
This new method has already been applied to the actual design
of sever al LSIs with satisfactory results. Moreover, the trial
proved a substantial performance improvement and a dramatic
decrease in design time as compared with conventional design
methods. NEC and NEC Electronics consider this method to be
effective in shortening the design period for large scale and high
speed LSIs, and are ready to apply the technology in-house to LSIs
for NEC’s products such as supercomputers (SX Series), enterprise
server products (NX 7700i Series) and platforms, allowing the
timely provision of high quality products to customers.
NEC presented the results of this research on the 27th of July
at the Design Automation Conference 2006 (DAC 2006), the world’s
largest international conference on system LSI design (July 23-28,
San Francisco, USA).
About NEC Corporation NEC Corporation (NASDAQ: NIPNY) is one
of the world's leading providers of Internet, broadband network and
enterprise business solutions ded icated to meeting the specialized
needs of its diverse and global base of customers. NEC delivers
tailored solutions in the key fields of co mputer, networking and
electron devices, by integrating its technical strengths in IT and
Networks, and by providing advanced semiconductor solutions through
NEC Electronics Corporation. The NEC Group employs more than
150,000 people worldwide and had net sales of approximately
4,825
billion yen (approx. $41.2 billion) in the fiscal year ended
March 2006.
About NEC Electronics NEC Electronics Corporation (TSE: 6723)
specializes in semiconductor products encompassing advanced
technology solutions for the high-end co mputing and broadband
networking markets, system solutions for the mobile handset, PC
peripherals, automotive and digi tal consumer markets, and platform
solutions for a wide range of customer applications. NEC
Electronics Corporation has 25 subsidiaries worldwide including NEC
Electronics America, Inc. (
http://www.am.necel.com/ ) and
NEC Electronics (Europe) GmbH (
http://www.eu.necel.com/ ). For
additional in formation about NEC Electronics worldwide, visit
http://www.necel.com/ .